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TDA4691T Datasheet(PDF) 6 Page - NXP Semiconductors |
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TDA4691T Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 26 page  September 1993 6 Philips Semiconductors Preliminary specification Sync Processor with Clock (SPC) TDA4691 50/60 Hz output This is an open-collector output, which is LOW if more than 287 lines/field are detected. SSC generator The SSC generator generates a 3 stage super-sandcastle pulse on an open-collector output, which is able to operate up to 12 volts. The blanking thresholds 2.5 V and 4.5 V are derived from the gap reference (point 16). Signal identification with Digital PLL (DPLL) The analog signal identification with output signal at pin 4 is completed with a DPLL. This PLL is able to lock on the separated sync although the 13.5 MHz VCO is not locked on the input signal. The ratio of the lock condition to the unlock condition influences the voltage at pin 5. The detector circuit of the analog signal identification block evaluates the voltages at pins 2 and 5. If the voltage at pin 5 reaches 4 V (most of the time the PLL is locked) pin 4 will be HIGH. The voltages at pins 2 and 5 together with the state of the V-logic set the operation state of the TDA4691. The TDA4691 is able to accommodate to different input conditions automatically. Some operation conditions can be set externally by influencing the voltages at pins 2 and 5: 1. Time constant T1 (fast) on: voltage at pin 2 is limited to 5 V (0 to 5 V). 2. Time constant T3 (slow) on: voltage at pin 5 is limited to 6.2 V (0 to 6.2 V). 3. Time constant T3 (slow) inoperative: voltage at pin 2 is limited between 4 V and 6.5 V. 4. Time constant T3 (slow) inoperative with input signal: voltage at pin 2 is limited to 6.5 V (0 to 6.5 V). 5. VCO frequency fixed to f0: pin 2 is set to ground (V2 < 1 V). Noise detector This block switches the time constant to ‘slow’ if on standard signal a certain noise level is reached. This noise level is measured in a small window inside the sync pulse. |
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