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93LC56 Datasheet(PDF) 10 Page - Microchip Technology |
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93LC56 Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 20 page  93LC46/56/66 DS21712B-page 10 2004 Microchip Technology Inc. 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE 3.1 Chip Select (CS) A high level selects the device. A low level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. 3.2 Serial Clock (CLK) The serial clock is used to synchronize the communica- tion between a master device and the 93LC46/56/66. Opcode, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don't care” if CS is low (device deselected). If CS is high, but Start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for Start condition). CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed (see instruction set truth table). CLK and DI then become “don't care” inputs waiting for a new Start condition to be detected. 3.3 Data In (DI) Data In is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. 3.4 Data Out (DO) Data Out is used in the Read mode to output data syn- chronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status infor- mation is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an erase or write operation has been initiated. The Status signal is not available on DO, if CS is held low or high during the entire write or erase cycle. In all other cases DO is in the High-Z mode. If status is checked after the write/erase cycle, a pull-up resistor on DO is required to read the Ready signal. 3.5 Organization (ORG) When ORG is connected to VCC, the (x16) memory organization is selected. When ORG is tied to VSS, the (x8) memory organization is selected. ORG can only be floated for clock speeds of 1 MHz or less for the (x16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to VCC or VSS. Name PDIP SOIC ROTATED TSSOP Description CS 1 1 3 Chip Select CLK 2 2 4 Serial Data Clock DI 3 3 5 Serial Data Input DO 4 4 6 Serial Data Output VSS 5 5 7 Ground ORG 6 6 8 Memory Configuration NU 7 7 1 Not Utilized Vcc 8 8 2 +1.8V to 5.5V Power Supply Note: CS must go low between consecutive instructions. |
Número de pieza similar - 93LC56 |
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Descripción similar - 93LC56 |
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