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TSC2004IYZKR Datasheet(PDF) 8 Page - Burr-Brown (TI) |
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TSC2004IYZKR Datasheet(HTML) 8 Page - Burr-Brown (TI) |
8 / 54 page www.ti.com TSC2004 SBAS408A – JUNE 2007 – REVISED AUGUST 2007 TIMING REQUIREMENTS: I 2C High-Speed Mode (f SCL = 3.4MHz) (1) All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V(2) to +3.6V, unless otherwise noted. 2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 μs Reset low time(3) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 μs SCL clock frequency fSCL 3.4 MHz Hold time (repeated) START condition tHD, STA 160 ns Low period of SCL clock tLOW 160 ns High period of the SCL clock tHIGH 60 ns Setup time for a repeated START condition tSU, STA 160 ns Data hold time tHD, DAT 0 70 ns Data setup time tSU, DAT 10 ns Rise time for SCL clock signal (receiving) tR Cb = total bus capacitance 10 40 ns Rise time for SDA clock signal (receiving) tR Cb = total bus capacitance 10 80 ns Fall time for SCL clock signal (receiving) tF Cb = total bus capacitance 10 40 ns Fall time for SDA clock signal (receiving) tF Cb = total bus capacitance 10 80 ns Fall time for both SDA and SCL clock signals tOF Cb = total bus capacitance 10 80 ns (transmitting) Setup time for STOP condition tSU, STO 160 ns Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 100 pF Pulse width of spike suppressed tSP 0 10 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Due to the low supply voltage of 1.2V and the wide temperature range of –40 °C to +85°C, the I2C system devices may not reach the maximum specification of I2C High-Speed mode, and fSCL may not reach 3.4Mhz. (3) Refer to Figure 36. 8 Submit Documentation Feedback |
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