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TDA8752 Datasheet(PDF) 3 Page - NXP Semiconductors |
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TDA8752 Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 36 page  1999 Mar 09 3 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage for R, G and B channels 4.75 5.0 5.25 V VDDD logic supply voltage for I2C-bus and 3-wire 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V VCCA(PLL) analog PLL supply voltage 4.75 5.0 5.25 V VCCO(PLL) output PLL supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 120 − mA IDDD logic supply current for I2C-bus and 3-wire − 1.0 − mA ICCD digital supply current − 40 − mA ICCO output stages supply current fCLK = 100 MHz; ramp input − 6 − mA ICCA(PLL) analog PLL supply current − 28 − mA ICCO(PLL) output PLL supply current − 5 − mA fCLK maximum clock frequency TDA8752/6 60 −− MHz TDA8752/8 100 −− MHz fref(PLL) PLL reference clock frequency 15 − 280 kHz fVCO VCO output clock frequency 12 − 100 MHz INL DC integral non linearity from analog input to digital output; full-scale; ramp input; fCLK = 100 MHz −±0.5 ±1.5 LSB DNL DC differential non linearity from analog input to digital output; full-scale; ramp input; fCLK = 100 MHz −±0.5 ±1.0 LSB ∆G amp/T amplifier gain stability as a function of temperature Vref = 2.5 V with 100 ppm/ °C maximum −− 200 ppm/ °C B amplifier bandwidth −3 dB; T amb =25 °C 250 −− MHz tset settling time of the ADC block plus AGC input signal settling time < 1 ns; Tamb =25 °C −− 6ns DRPLL PLL divider ratio 100 − 4095 Ptot total power consumption fCLK = 100 MHz; ramp input − 1.0 − W jPLL(rms) maximum PLL phase jitter (RMS value) fref = 66.67 kHz; fCLK = 100 MHz − 0.3 − ns |
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