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TDA8960 Datasheet(PDF) 10 Page - NXP Semiconductors |
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TDA8960 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 32 page  1999 Jun 14 10 Philips Semiconductors Preliminary specification ATSC 8-VSB demodulator and decoder TDA8960 The equalizer has been designed to correct a maximum pre-echo of 2.32 µs and a maximum post-echo of 10.50 µs. The equalizer uses an overlapping DFE to reduce the effects of co-channel interference. The equalizer has been optimized to have a typical acquisition time of 12 training sequences, which corresponds to approximately 290 ms. The acquisition time has been defined as the time when the output signal-to-noise ratio reaches the Threshold Of Visibility (TOV). The ATSC defines a TOV of 14.9 dB for 8-VSB. Based on the training signal and the output of the equalizer the Mean Square Error (MSE) signal is generated. This 16-bit value is used to control the channel adaptation process and is available though I2C-bus control. Control The TDA8960 contains a complicated finite state machine. This state machine controls the sequence of operations that must be performed when a valid VSB data signal is detected in order for it to be properly decoded into a stream of MPEG-2 transport packets. The following steps have to take place: 1. The external tuner is directed to lock to a specified channel frequency. A VSB signal is present. 2. The tuner AGC locks to an acceptable signal gain. 3. The coarse AGC of the TDA8960 locks to acceptable A/D converter gain. 4. The timing and carrier recovery loops lock to the symbol clock and the carrier frequency. 5. The segment sync pattern is detected. The segment sync lock is acquired. 6. The fine AGC locks. 7. The field sync pattern is detected. The MSE of the received field sync training sequence is determined. 8. The equalizer uses subsequent training sequences to adapt itself to the channel conditions. 9. The equalizer adapts to the point that the MSE of the training sequence is sufficiently small. The trellis decoding, convolutional de-interleaving and Reed Solomon decoding processes all begin. 10. Valid MPEG-2 transport packets are generated. The finite state machine consists of three states. After a reset has been applied, the state machine starts in state 0. STATE 0: CHANNEL ACQUISITION In this state either no channel signal is present or a channel signal is being acquired. The AGC, timing recovery and carrier recovery loops must first lock onto it. If the segment sync lock is lost, pin LOCKINDIC is LOW, or a hardware reset is applied to the VSB demodulator, the finite state machine returns to state 0. STATE 1: EQUALIZER TRAINING The finite state machine remains in state 1 until the MSE of the equalized training sequence falls below a certain threshold. It should be noted that in state 1 the back-end is continuously reset to make sure that after the demodulator has locked onto a signal, the trellis decoder and following processing blocks begin at the start of the next complete data field. By means of I2C-bus registers 01H and 02H the MSE value of the equalizer can be read. This value can be used for applications such as antenna pointing. STATE 2: NORMAL OPERATION Normally the state machine would remain in state 2 as long as no synchronization error occurs. If the MSE of the equalized training sequence is exceeded for more than 100 ms, the equalizer is reset for one symbol period and the adaptation process starts again. If the demodulator is in this state, the EQLOCKINDIC pin signal goes up. The value of this signal can also be read through the I2C-bus. |
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