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ADS7863IRGER Datasheet(PDF) 8 Page - Burr-Brown (TI) |
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ADS7863IRGER Datasheet(HTML) 8 Page - Burr-Brown (TI) |
8 / 30 page www.ti.com CLOCK CONVST 12ns Cyc e l 1 Cyc e l 2 A B C 12ns TBD TBD TIMING REQUIREMENTS (1) ADS7863 SBAS383 – JUNE 2007 TIMING CHARACTERISTICS (continued) NOTE: All CONVST commands that occur more than 12ns before the rising edge of cycle ‘1’ of the external clock (Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur TBDns after the rising edge of cycle ‘1’ or 12ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge of cycle ‘2’. All CONVST commands that occur TBDns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from LOW to HIGH in the region 12ns prior to the rising edge of the CLOCK and TBDns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge. Figure 2. CONVST Timing Over recommended operating free-air temperature range at –40 °C to +125°C, AV DD = 5V, and BVDD = 2.7V to 5V, unless otherwise noted. ADS7863 SYMBOL PARAMETER COMMENTS MIN MAX UNIT tCONV Conversion time fCLOCK = 24MHz 541.67 ns tACQ Acquisition time fCLOCK = 24MHz 125 ns fCLOCK CLOCK frequency See Figure 1 1 24 MHz TCLOCK CLOCK period See Figure 1 41.67 1000 ns tCKL CLOCK low time See Figure 1 5 ns tCKH CLOCK high time See Figure 1 5 ns t1 CONVST high time See Figure 1 15 ns t2 SDI setup time to CLOCK falling edge See Figure 1 10 ns t3 SDI hold time to CLOCK falling edge See Figure 1 5 ns t4 RD high setup time to CLOCK falling edge See Figure 1 10 ns t5 RD high hold time to CLOCK falling edge See Figure 1 5 ns t6 CONVST low time See Figure 1 15 ns t7 RD low time relative to CLOCK falling edge See Figure 1 15 ns t8 CS low to SDOx valid See Figure 1 20 ns SDOx data setup time to CLOCK falling t9 See Figure 1 25 ns edge t10 SDOx data hold time to CLOCK falling edge See Figure 1 5 ns CONVST setup time to rising edge of t11 See Figure 1 12 ns CLOCK t12 CLOCK rising edge to BUSY low delay See Figure 1 3 ns t13 CS low to RD high delay See Figure 1 10 ns (1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. 8 Submit Documentation Feedback |
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