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COP8SBE9 Datasheet(PDF) 17 Page - National Semiconductor (TI) |
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COP8SBE9 Datasheet(HTML) 17 Page - National Semiconductor (TI) |
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17 / 70 page  4.0 Functional Description (Continued) = 0 WATCHDOG feature enabled. G1 pin is WATCHDOG output with weak pullup. Bit 1 = 1 HALT mode disabled. = 0 HALT mode enabled. Bit 0 = 1 Execution following RESET will be from Flash Memory. = 0 Flash Memory is erased. Execution following RE- SET will be from Boot ROM with the MICROWIRE/ PLUS ISP routines. The COP8 assembler defines a special ROM section type, CONF, into which the Option Register data may be coded. The Option Register is programmed automatically by pro- grammers that are certified by National. The user needs to ensure that the FLEX bit will be set when the device is programmed. The following examples illustrate the declaration of the Op- tion Register. Syntax: [label:].sect config, conf .db value ;1 byte, ;configures ;options .endsect Example: The following sets a value in the Option Register and User Identification for a COP8SBE9HVA7. The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled and execution will commence from Flash Memory. .chip 8SBE .sect option, conf .db 0x01 ;wd, halt, flex .endsect ... .end start Note: All programmers certified for programming this family of parts will support programming of the Option Register. Please contact National or your device programmer supplier for more information. 4.6 SECURITY The device has a security feature which, when enabled, prevents external reading of the Flash program memory. The security bit in the Option Register determines, whether se- curity is enabled or disabled. If the security feature is dis- abled, the contents of the internal Flash Memory may be read by external programmers or by the built in MICROWIRE/PLUS serial interface ISP. Security must be enforced by the user when the contents of the Flash Memory are accessed via the user ISP or Virtual EE- PROM capability. If the security feature is enabled, then any attempt to exter- nally read the contents of the Flash Memory will result in the value FF (hex) being read from all program locations (except the Option Register). In addition, with the security feature enabled, the write operation to the Flash program memory and Option Register is inhibited. Page Erases are also inhib- ited when the security feature is enabled. The Option Reg- ister is readable regardless of the state of the security bit by accessing location FFFF (hex). Mass Erase Operations are possible regardless of the state of the security bit. The security bit can be erased only by a Mass Erase of the entire contents of the Flash unless Flash operation is under the control of User ISP functions. Note: The actual memory address of the Option Register is 0x3FFF (hex), however the MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the Option Register when the Flash Memory is secured. The entire Option Register must be programmed at one time and cannot be rewritten without first erasing the entire last page of Flash Memory. 4.7 RESET The device is initialized when the RESET pin is pulled low or the On-chip Brownout Reset is activated. The Brownout Reset feature is not available on the COP8SDE9. The following occurs upon initialization: Port A: TRI-STATE (High Impedance Input) Port B: TRI-STATE (High Impedance Input) Port G: TRI-STATE (High Impedance Input). Exceptions: If Watchdog is enabled, then G1 is Watchdog output. G0 and G2 have their weak pull-up enabled during RESET. Port H: TRI-STATE (High Impedance Input) Port L: TRI-STATE (High Impedance Input) PC: CLEARED to 0000 PSW, CNTRL and ICNTRL registers: CLEARED SIOR: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on T2CNTRL: CLEARED HSTCR: CLEARED ITMR: Cleared except Bit 6 (HSON) = 1 Accumulator, Timer 1 and Timer 2: RANDOM after RESET WKEN, WKEDG: CLEARED WKPND: RANDOM SP (Stack Pointer): Initialized to RAM address 06F Hex B and X Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on S Register: CLEARED RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on USART: PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit which is set to one. ISP CONTROL: 20032711 FIGURE 8. Reset Logic www.national.com 17 |
Número de pieza similar - COP8SBE9 |
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Descripción similar - COP8SBE9 |
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