Mask Set Errata for 9S08QG8, Mask 3M77B

6

Freescale Semiconductor

With common HCS08 bus frequencies, practical PWM frequencies, and reasonable resolution

requirements, there is enough speed and flexibility in the TPM system so this workaround should work

well with all except the most unusual application systems.

Another workaround would be to limit the range of allowed values in the channel value register so it does

not include the TPMxMODH:TPMxMODL or (TPMxMODH:TPMxMODL – 1) values. Not all applications

require the range to include these values.

Case 3: Center-Aligned PWM

TPMxCnVH:TPMxCnVL Changed from 0x0000 to a Non-Zero Value

Description

This case occurs only while the counter is counting down (first half of the center-aligned PWM period).

The PWM output changes to the active level at the middle of the current PWM period as the count reaches

0x0000 instead of waiting for the start of a new PWM period to begin using the new duty cycle setting.

Workaround

Use a negative channel value instead of 0x0000 to produce 0% duty cycle. This can be done by checking

any value that is about to be written to the channel value registers, and then decrementing the 16-bit value

or the high-order byte of this value before writing it to the channel value registers. This produces the

desired 0% duty cycle and it avoids the problems related to a zero in the channel value registers.

Case 4: Center-Aligned PWM

TPMxCnVH:TPMxCnVL Changed from a Non-Zero Value to 0x0000

Description

This case occurs only while the counter is counting up (second half of the center-aligned PWM period)

but before the count reaches the channel value setting in TPMxCnVH:TPMxCnVL. The PWM output

remains at the active level until the end of the current PWM period instead of finishing the current PWM

period using the old channel value setting.

Workaround

Use a negative channel value instead of 0x0000 to produce 0% duty cycle. This can be done by checking

any value that is about to be written to the channel value registers, and then decrement the 16-bit value

or the high-order byte of this value before writing it to the channel value registers. This produces the

desired 0% duty cycle and it avoids the problems related to a zero in the channel value registers.