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AS6C1008 Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation |
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AS6C1008 Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation |
6 / 14 page WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW tWR tAS (4) TOW CE# tAW Address tWC CE2 WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# tWP tCW CE# tWR tAS tAW Address tWC CE2 Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. ® February 2007 128K X 8 BIT LOW POWER CMOS SRAM AS6C1008 02/February/07, v 1.0 Alliance Memory Inc. Page 6 of 14 |
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