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74AUP1G373GW Datasheet(PDF) 10 Page - NXP Semiconductors |
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74AUP1G373GW Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 22 page 74AUP1G373_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 20 July 2007 10 of 22 NXP Semiconductors 74AUP1G373 Low-power D-type transparent latch; 3-state CL = 15 pF tpd propagation delay D to Q; see Figure 7 [2] VCC = 0.8 V - 33.3 - - - - - ns VCC = 1.1 V to 1.3 V 3.5 8.6 16.9 3.2 17.5 3.2 19.2 ns VCC = 1.4 V to 1.6 V 3.1 5.9 9.6 2.7 10.5 2.7 11.6 ns VCC = 1.65 V to 1.95 V 2.6 4.8 7.6 2.2 8.5 2.2 9.3 ns VCC = 2.3 V to 2.7 V 2.5 3.8 5.5 2.2 5.9 2.2 6.5 ns VCC = 3.0 V to 3.6 V 2.2 3.5 4.9 1.8 5.5 1.8 6.0 ns LE to Q; see Figure 8 [2] VCC = 0.8 V - 32.4 - - - - - ns VCC = 1.1 V to 1.3 V 3.3 8.4 17.3 3.0 18.0 3.0 19.8 ns VCC = 1.4 V to 1.6 V 3.0 5.7 9.7 2.5 10.7 2.5 11.8 ns VCC = 1.65 V to 1.95 V 2.5 4.6 7.4 2.2 8.3 2.2 9.1 ns VCC = 2.3 V to 2.7 V 2.3 3.6 5.3 2.0 5.9 2.0 6.4 ns VCC = 3.0 V to 3.6 V 2.1 3.2 4.6 1.8 5.1 1.8 5.6 ns ten enable time OE to Q; see Figure 10 [3] VCC = 0.8 V - 24.2 - - - - - ns VCC = 1.1 V to 1.3 V 2.8 5.8 13.0 2.6 16.0 2.6 16.1 ns VCC = 1.4 V to 1.6 V 2.7 4.5 7.6 2.3 8.2 2.3 8.6 ns VCC = 1.65 V to 1.95 V 2.4 3.9 6.1 2.2 6.7 2.2 7.0 ns VCC = 2.3 V to 2.7 V 2.1 3.4 4.8 2.1 5.1 2.1 5.3 ns VCC = 3.0 V to 3.6 V 2.3 3.3 4.4 2.1 4.7 2.1 4.9 ns tdis disable time OE to Q; see Figure 10 [4] VCC = 0.8 V - 12.6 - - - - - ns VCC = 1.1 V to 1.3 V 3.3 5.5 10.2 3.3 10.4 3.3 10.6 ns VCC = 1.4 V to 1.6 V 2.9 4.3 7.0 2.7 7.4 2.7 7.6 ns VCC = 1.65 V to 1.95 V 3.1 4.6 7.4 3.1 7.7 3.1 7.9 ns VCC = 2.3 V to 2.7 V 2.1 3.3 5.2 2.3 5.4 2.3 5.6 ns VCC = 3.0 V to 3.6 V 3.2 4.5 6.6 3.1 6.8 3.1 6.9 ns Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions 25 °C −40 °C to +125 °C Unit Min Typ[1] Max Min (85 °C) Max (85 °C) Min (125 °C) Max (125 °C) |
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