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FM25CL64 Datasheet(PDF) 2 Page - Ramtron International Corporation

No. de pieza FM25CL64
Descripción Electrónicos  64Kb FRAM Serial 3V Memory
Download  13 Pages
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Fabricante Electrónico  RAMTRON [Ramtron International Corporation]
Página de inicio  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM25CL64 Datasheet(HTML) 2 Page - Ramtron International Corporation

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FM25CL64 - Automotive Temp.
Rev. 3.0
May 2007
Page 2 of 13
Instruction Decode
Clock Generator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
`
2,048 x 32
FRAM Array
13
Data I/O Register
8
Nonvolatile Status
Register
3
WP
CS
HOLD
SCK
SO
SI
Figure 1. Block Diagram
Pin Descriptions
Pin Name
I/O
Description
/CS
Input
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
SCK
Input
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 16 MHz and may be interrupted at
any time.
/HOLD
Input
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
/WP
Input
Write Protect: This active low pin prevents write operations to the status register. This
is critical since other write protection features are controlled through the status
register. A complete explanation of write protection is provided below. *Note that the
function of /WP is different from the FM25040 where it prevents all writes to the part.
SI
Input
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
SO
Output
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
VDD
Supply
Power Supply (3.0V to 3.6V)
VSS
Supply
Ground


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