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CAT863TTBI-G Datasheet(PDF) 2 Page - Catalyst Semiconductor |
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CAT863TTBI-G Datasheet(HTML) 2 Page - Catalyst Semiconductor |
2 / 9 page CAT853, CAT863, CAT859, CAT869 2 Doc. No. 3026, Rev. B © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ABSOLUTE MAXIMUM RATINGS(1) Any pin with respect to ground -0.3V to +6.0V Input Current, VCC 20mA Output Current, RESET 20mA Rate of Rise, VCC 100V/μs Continuous Power Dissipation Derate 4mW/ºC above 70ºC (SOT23) 320 mW Operating Temperature Range -40ºC to +85ºC Storage Temperature Range -65ºC to +105ºC Lead Soldering Temperature (10 sec) 300ºC Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. ELECTRICAL CHARACTERISTICS VCC = Full range, TA = -40ºC to +85ºC unless otherwise noted. Typical values at TA = +25ºC and VCC = 3.3V for the T/S versions, VCC = 5V for the M version. Parameter Symbol Conditions Min Typ(1) Max Units VCC Range TA = 0ºC to +70ºC 1.0 5.5 V TA = -40ºC to +85ºC 1.2 5.5 Supply Current ICC TA = -40ºC to +85ºC VCC < 3.6V, S/T 6 15 μA Reset Threshold Voltage VTH T Threshold TA = +25ºC 3.04 3.08 3.11 V TA = -40ºC to +85ºC 3.00 3.15 S Threshold TA = +25ºC 2.89 2.93 2.96 TA = -40ºC to +85ºC 2.85 3.00 M Threshold TA = +25ºC 4.31 4.38 4.45 TA = -40ºC to +85ºC 4.25 4.50 Reset Threshold Tempco 30 ppm/ºC VCC to Reset Delay VCC = VTH to (VTH - 100 mV) 20 μs Reset Active Timeout Period TA = -40ºC to +85ºC 140 240 460 ms RESET Output Voltage Low VOL VCC = VTH min, ISINK = 1.2mA 0.4 V VCC > 1.0V, ISINK = 50μA 0.3 RESET Output Voltage High VOH VCC = VTH max, ISOURCE = -500μA (for CAT859/869 only) 0.8 VCC V Note: (1) Production testing done at TA = +25ºC; limits over temperature guaranteed by design only. |
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