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CAT25640VI-GT3 Datasheet(PDF) 7 Page - Catalyst Semiconductor

No. de pieza CAT25640VI-GT3
Descripción Electrónicos  64-Kb SPI Serial CMOS EEPROM
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Fabricante Electrónico  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT25640VI-GT3 Datasheet(HTML) 7 Page - Catalyst Semiconductor

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CAT25640
© Catalyst Semiconductor, Inc.
7
Doc. No. MD-1128 Rev. B
Characteristics subject to change without notice
SCK
SI
SO
00
0
0
00
10
D7 D6 D5 D4 D3 D2 D1 D0
01234
5678
21
22
23
24
25
26
27
28
29
30
31
CS
OPCODE
* Please check the Byte Address Table (Table 5)
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
AN
A0
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16-bit
address and data as shown in Figure 4. Only 13
significant address bits are used by the CAT25640.
The rest are don’t care bits, as shown in Table 5.
Internal programming will start after the low to high CS
¯¯
transition.
During
an
internal
write
cycle,
all
commands, except for RDSR (Read Status Register)
will be ignored. The RDY
¯¯¯¯ bit will indicate if the internal
write cycle is in progress (RDY
¯¯¯¯ high), or the the
device is ready to accept commands (RDY
¯¯¯¯ low).
Page Write
After sending the first data byte to the CAT25640, the
host may continue sending data, up to a total of 64
bytes, according to timing shown in Figure 5. After
each data byte, the lower order address bits are
automatically incremented, while the higher order
address bits (page address) remain unchanged. If
during this process the end of page is exceeded, then
loading will “roll over” to the first byte in the page, thus
possibly overwriting previoualy loaded data. Following
completion of the write cycle, the CAT25640 is
automatically returned to the write disable state.
Table 5. Byte Address
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulses
CAT25640
A12 - A0
A15 - A13
16
Figure 4. Byte WRITE Timing
Note:
Dashed Line = mode (1, 1) - - - - - -
Figure 5. Page WRITE Timing
Note:
Dashed Line = mode (1, 1) - - - - - -
SCK
SI
SO
00
0
0
00
10
BYTE ADDRESS*
Data
Byte 1
012345678
21
22
23 24-31 32-39
Data
Byte 2
Data
Byte 3
Data Byte N
CS
OPCODE
7..1
0
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
DATA IN
HIGH IMPEDANCE
AN
A0
*Please check the Byte Address Table. (Table 5)


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