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ADSP-BF561SBBCZ-6A2 Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-BF561SBBCZ-6A2 Datasheet(HTML) 2 Page - Analog Devices |
2 / 64 page Rev. B | Page 2 of 64 | June 2007 ADSP-BF561 TABLE OF CONTENTS General Description ................................................. 3 Portable Low Power Architecture ............................. 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 DMA Controllers .................................................. 8 Watchdog Timer .................................................. 8 Timers ............................................................... 9 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Port ......................... 9 UART Port .......................................................... 9 Programmable Flags (PFx) .................................... 10 Parallel Peripheral Interface ................................... 10 Dynamic Power Management ................................ 11 Voltage Regulation .............................................. 12 Voltage Regulator Layout Guidelines .................... 12 Clock Signals ..................................................... 13 Booting Modes ................................................... 14 Instruction Set Description ................................... 14 Development Tools ............................................. 15 Designing an Emulator-Compatible Processor Board .. 16 Related Documents ............................................. 16 Pin Descriptions .................................................... 17 Specifications ........................................................ 20 Operating Conditions .......................................... 20 Electrical Characteristics ....................................... 20 Absolute Maximum Ratings .................................. 21 Package Information ........................................... 21 ESD Sensitivity ................................................... 21 Timing Specifications .......................................... 22 Clock and Reset Timing .................................... 23 Asynchronous Memory Read Cycle Timing ........... 24 Asynchronous Memory Write Cycle Timing .......... 25 SDRAM Interface Timing .................................. 26 External Port Bus Request and Grant Cycle Timing .. 27 Parallel Peripheral Interface Timing ..................... 28 Serial Ports ..................................................... 32 Serial Peripheral Interface (SPI) Port— Master Timing ............................................. 35 Serial Peripheral Interface (SPI) Port— Slave Timing ............................................... 36 Universal Asynchronous Receiver Transmitter (UART) Port—Receive and Transmit Timing ................. 37 Programmable Flags Cycle Timing ....................... 38 Timer Cycle Timing .......................................... 39 JTAG Test and Emulation Port Timing .................. 40 Output Drive Currents ......................................... 41 Power Dissipation ............................................... 42 Test Conditions .................................................. 42 Environmental Conditions .................................... 44 256-Ball CSP_BGA Ball Assignment ........................... 46 256-Ball CSP_BGA Ball Assignment ........................... 51 297-Ball PBGA ball assignment .................................. 56 Outline Dimensions ................................................ 61 Ordering Guide ..................................................... 64 REVISION HISTORY 4/07—Changes from Rev. A to Rev. B Added Text to Serial Ports (SPORTs) ............................. 9 Changed Font in Formula in Power Savings ...................12 Complete Rewrite of Operating Conditions ....................20 Complete Rewrite of Electrical Characteristics ................20 Edit to Figure Asynchronous Memory Read Cycle Timing .24 Edit to Figure Asynchronous Memory Write Cycle Timing 25 Deleted References to Temperature in Figures in Output Drive Currents ..........................................41 Moved Data to Operating Conditions and Rewrote Power Dissipation ..................................42 Deleted References to Temperature in Figures in Test Conditions ...................................................42 Added figures for 256-Ball CSP_BGA Ball Configuration (Top View) ....................................................................50 Added figure 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-4).............................................61 Added Models to Ordering Guide ................................64 5/06—Changes from Rev. 0 to Rev. A 1/05—Initial version |
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