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IN

IN

IN

PG

BIAS

OUT

OUT

OUT

NC

FB

TPS74201

6

7

8

9

10

20

19

18

17

16

5

5QFN(RGW)

´

Package

TopView

¾

7-Lead

DDPAK(KTW)

Surface-Mount

OUT

GND BIAS

IN

FB

SS

1

2

3

4

5

6

EN

7

PIN DESCRIPTIONS

TPS74201

SBVS064F – DECEMBER 2005 – REVISED OCTOBER 2007

NAME

KTW (DDPAK)

RGW (QFN)

DESCRIPTION

IN

5

5–8

Unregulated input to the device.

Enable pin. Driving this pin high enables the regulator. Driving this pin low puts

EN

7

11

the regulator into shutdown mode. This pin must not be left floating.

Soft-Start pin. A capacitor connected on this pin to ground sets the start-up

SS

1

15

time. If this pin is left floating, the regulator output soft-start ramp time is

typically 100

μs.

BIAS

6

10

Bias input voltage for error amplifier, reference, and internal control circuits.

Power-Good (PG) is an open-drain, active-high output that indicates the status

PG

N/A

9

low-impedance state. A pull-up resistor from 10k

Ω to 1MΩ should be connected

from this pin to a supply up to 5.5V. The supply can be higher than the input

voltage. Alternatively, the PG pin can be left floating if output monitoring is not

necessary.

This pin is the feedback connection to the center tap of an external resistor

FB

2

16

divider network that sets the output voltage. This pin must not be left floating.

OUT

3

1, 18–20

Regulated output voltage. No capacitor is required on this pin for stability.

No connection. This pin can be left floating or connected to GND to allow better

NC

N/A

2–4, 13, 14, 17

thermal contact to the top-side plane.

GND

4

12

Ground

PAD/TAB

Should be soldered to the ground plane for increased thermal performance.

Copyright © 2005–2007, Texas Instruments Incorporated

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5

Product Folder Link(s): TPS74201