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TPS51100DGQG4 Datasheet(PDF) 6 Page - Texas Instruments

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No. de pieza TPS51100DGQG4
Descripción Electrónicos  3-A SINK/SOURCE DDR TERMINATION REGULATOR
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS51100DGQG4 Datasheet(HTML) 6 Page - Texas Instruments

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TPS51100
SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005
6
www.ti.com
DETAILED DESCRIPTION
VTT SINK/SOURCE REGULATOR
The TPS51100 is a 3-A sink/source tracking termination regulator designed specially for low-cost, low external
components system where space is at premium such as notebook PC applications. TPS51100 integrates high-
performance low−dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT
linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to
keep tracking to the VTTREF within
±40 mV at all conditions including fast load transient. To achieve tight
regulation with minimum effect of trace resistance, a remote sensing terminal, VTTSNS, should be connected
to the positive node of VTT output capacitor(s) as a separate trace from the high current line from VTT.
VTTREF REGULATOR
The VTTREF block consists of an on-chip 1/2 divider, LPF and buffer. This regulator can source current up to
10 mA. Bypass VTTREF to GND using a 0.1-
µF ceramic capacitor to ensure stable operation.
Soft-Start
The soft-start function of the VTT is achieved via a current clamp, allowing the output capacitors to be charged
with low and constant current that gives linear ramp up of the output voltage. The current limit threshold is
changed in two stages using an internal powergood signal. When VTT is outside the powergood threshold, the
current limit level is 2.2 A. When VTT rises above (VTTREF − 5%) or falls below (VTTREF + 5%) the current
limit level switches to 3.8 A. The thresholds are typically VTTREF
±5% (from outside regulation to inside) and
±10% (when it falls outside). The soft-start function is completely symmetrical and it works not only from GND
to VTTREF voltage, but also from VDDQ to VTTREF voltage. Note that the VTT output is in a high impedance
state during the S3 state (S3 = low, S5 = high) and its voltage can be up to VDDQ voltage depending on the
external condition. Note that VTT does not start under a full load condition.
S3, S5 Control and Soft-Off
The S3 and S5 terminals should be connected to SLP_S3 and SLP_S5 signals respectively. Both VTTREF and
VTT are turned on at S0 state (S3 = high, S5 = high). VTTREF is kept alive while VTT is turned off and left high
impedance in S3 state (S3 = low, S5 = high). Both VTT and VTTREF outputs are turned off and discharged to
the ground through internal MOSFETs during S4/S5 state (both S3 and S5 are low).
Table 1. S3 and S5 Control Table
STATE
S3
S5
VTTREF
VTT
S0
H
H
1
1
S3
L
H
1
0 (high−Z)
S4/S5
L
L
0 (discharge)
0 (discharge)
(In case S3 is forced H and S5 to L, VTTREF is discharged and VTT is at High−Z state. This condition is NOT
recommended.)
VTT Current Protection
The LDO has a constant overcurrent limit (OCL) at 3.8 A. This trip point is reduced to 2.2 A before the output
voltage comes within
±5% of the target voltage or goes outside of ±10% of the target voltage.


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