PAGE . 3

REV.0-JUN.15.2005

1SMB3EZ6.8~1SMB3EZ100

APPLICATION NOTE:

Since t he actual voltage available from a g iven zener diode is temperature dependent, i t i s n ecessary to determinejunction

temperature under any s et of operating conditions in order to calculate i ts value. The f ollowing procedure i s r ecommended:

Lead Te mperature, T , should be determined from:

T= L A P + T

L i s t he lead-to-ambient thermal r esistance ( C/W) and P d i s t he power dissipation. The v alue for L will vary and depends

on the device m ounting method.

L i s g enerally 30-40 C /W for t he various clips and t ie points i n c ommon u se and for printed

circuit board wiring.

The t emperature o f t he lead can also b e m easured using a t hermocouple placed on the l ead as close a s p ossible to the t ie poi n

The t hermal m ass c onnected t o t he tie point is normally large enough so that it will not s ignificantly respond to heat surges

generated in the diode as a r esult of pulsed operation once s teady-state c onditions are achieved. Using the m easured value of

TL, t he junction temperature m ay be determined by:

T= T + T

T

i s t he increase i n j unction temperature above t he lead temperature and may b e f ound from Figure 2 f or a t rain of power puls

or from Figure 1 0 f or dc power.

T= J P

For w orst-case design, using expected l imits o f I , l imits o f P and the e xtremes o f T ( T ) m ay be estimated. Changes in volta

V , can t hen be found from:

V= V

T

V , the z ener voltage temperature c oefficient, i s f ound from Figures 5 a nd 6.

Under high power-pulse operation, the z ener voltage will vary with time and may a lso b e a ff ected s ignificantly by the z ener resis

For b est r egulation, keep current excursions as low a s p ossible.

Data o f F igure 2 s hould not be used to compute s urge capa-bility. Surge l imitations are given in Figure 3 . T hey are lower than w

be expected b y c onsidering only junction temperature, as current crowding effects c ause t emperatures to be extremely high in s

spots r esulting in device degradation should the l imits o f F igure 3 b e e xceeded.

L

LD

A

A

A

A

JL

JL

JL

Z

q

q

q

q

D

D

Dq

D

Dq

D

q

O

O

JL

L

D

ZD

J

J

Z

ZJ