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CAT1232 Datasheet(PDF) 5 Page - Catalyst Semiconductor

No. de Pieza. CAT1232
Descripción  5V and 3.3V Supply Monitor, Watchdog Timer, Manual Reset, with Active High & Low Resets
Descarga  12 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT1232 Datasheet(HTML) 5 Page - Catalyst Semiconductor

 
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CAT1232, CAT1832
APPLICATION INFORMATION
SUPPLY VOLTAGE MONITOR
Reset Signal Polarity and Output Stage Structure
RESET
¯¯¯¯¯¯ is an active LOW signal. It is developed with
an open drain driver in the CAT1232LP. A pull-up
resistor is required, typical values are 10kΩ to 50kΩ.
The CAT1832 uses a CMOS push-pull output stage
for the RESET
¯¯¯¯¯¯.
RESET is an active High signal developed by a
CMOS push-pull output stage and is the logical
opposite to RESET
¯¯¯¯¯¯.
Trip Point Tolerance Selection
The TOL input is used to select the VCC trip point
threshold. This selection is made connecting the
TOL input to ground or V
CC. Connecting TOL to
Ground makes the V
CC trip threshold 4.62V for the
CAT1232LP and 2.88V for the CAT1832.
Connecting TOL to V
CC makes the VCC trip threshold
4.37V for the CAT1232LP and 2.55V for the
CAT1832.
After VCC has risen above the trip point set by TOL,
RESET and RESET
¯¯¯¯¯¯remain active for a minimum time
period of 250ms.
On power-down, once V
CC
falls below the reset
threshold the RESET outputs will remain active and
are guaranteed valid down to a V
CC level of 1.0V.
Trip Point Voltage (V)
Tolerance
Select
Voltage
Trip Point
Tolerance
MIN
NOMINAL
MAX
CAT1232LP
TOL = V
10 %
4.25
4.37
4.49
CC
CAT1232LP
TOL = GND
5 %
4.50
4.62
4.74
CAT1832
TOL = V
20 %
2.47
2.55
2.64
CC
CAT1832
TOL = GND
10 %
2.80
2.88
2.97
Manual Reset Operation
Push-button input, PBRST
¯¯¯¯¯¯, allows the user to issue
reset signals. The pushbutton input is debounced and
is pulled high through an internal 40kΩ resistor.
When PBRST
¯¯¯¯¯¯ is held low for the minimum time of
20ms, both resets become active and remain active
for a minimum time period of 250ms after PBRST
returns high.
No external pull-up resistor is required, since PBRST
¯¯¯¯¯¯
is pulled high by an internal 40kΩ resistor.
PBRST
¯¯¯¯¯¯ can be driven from a TTL or CMOS logic line
or short-ed to ground with a mechanical switch.
Figure 1. Timing Diagram: Power Up
Figure 2. Timing Diagram: Power Down
VCCTP(MAX)
VCCTP
VCCTP(MIN)
VCC
RESET
RESET
tF
VOH
VOL
tRPD
VCCTP(MAX)
VCCTP
VCCTP(MIN)
VCC
RESET
RESET
tR
tRPU
VOH
VOL
© Catalyst Semiconductor, Inc.
5
Doc. No. MD-3018 Rev. D
Characteristics subject to change without notice


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