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SM59264C40 Datasheet(PDF) 6 Page - SyncMOS Technologies,Inc |
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SM59264C40 Datasheet(HTML) 6 Page - SyncMOS Technologies,Inc |
6 / 36 page SyncMOS Technologies International, Inc. SM59264 8-Bits Micro-controller with 128KB flash & 1KB RAM & TWSI & SPWM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. Ver 2.1 SM59264 08/2006 6 C5H TWSIRxD 00H TWSIRxD7 TWSIRxD6 TWSIRxD5 TWSIRxD4 TWSIRxD3 TWSIRxD2 TWSIRxD1 TWSIRxD0 A9H IE1 00 ETWSI AAH IFR 00 TWSIF BAH IP1 00 PTWSI C8H T2CON 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 C9H T2MOD ******00 * * * * * * T2OE DCEN D8H P4 ****1111 P4.3 P4.2 P4.1 P4.0 F4H ISPFAH 00H FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8 F5H ISPFAL 00H FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 F6H ISPFD 00H FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 F7H ISPC 0*0***00 START FAU0 F1 F0 Extension Function Description 1. Memory Structure The SM59264 is the general 8052 hardware core to integrate the expanded 768 byte data RAM, 64KB flash program memory with ISP function module and 64KB data flash as a single chip micro controller. Its memory structure follows general 8052 structure plus SM59264 proprietary external RAM structure. 1.1 Program Memory The SM59264 has 64K byte on-chip flash memory which used as general program memory, on which include up to 4K byte specific ISP service program memory space. The address range for the 64K byte is $0000 to $FFFF. The address range for the ISP service program is $F000 to $FFFF. The ISP service program size can be partitioned as N blocks of 512 byte (N=0 to 8). When N=0 means no ISP service program space available, total 64K byte memory used as program memory. When N=1 means memory address $FE00 to $FFFF reserved for ISP service program. When N=2 means memory address $FC00 to FFFF reserved for ISP service program,...etc. Value N can be set and programmed into SM59264 by writer. 1.1.1 Program Code Security MOVC instruction executed from external program memory space will not be able to fetch internal codes from on chip program memory after the chip is protected on the Writer. |
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