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74AHCU04D Datasheet(PDF) 2 Page - NXP Semiconductors |
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74AHCU04D Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 14 page 74AHCU04_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 14 November 2007 2 of 14 NXP Semiconductors 74AHCU04 Hex inverter 4. Functional diagram 5. Pinning information 5.1 Pin description Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one inverter) mna342 1A 1Y 1 2 2A 2Y 3 4 3A 3Y 5 6 4A 4Y 9 8 5A 5Y 11 10 6A 6Y 13 12 1 1 2 mna343 3 1 4 5 1 6 9 1 8 11 1 10 13 1 12 mna045 AY (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 04 1A VCC 1Y 6A 2A 6Y 2Y 5A 3A 5Y 3Y 4A GND 4Y 001aac441 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aac442 04 GND(1) Transparent top view 3Y 4A 3A 5Y 2Y 5A 2A 6Y 1Y 6A 6 9 5 10 4 11 3 12 2 13 terminal 1 index area Table 2. Pin description Symbol Pin Description 1A 1 data input 1Y 2 data output 2A 3 data input 2Y 4 data output |
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