74AUP2G80_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 1 August 2007

11 of 18

NXP Semiconductors

74AUP2G80

Low-power dual D-type flip-flop; positive-edge trigger

12. Waveforms

Measurement points are given in Table 9.

Fig 7.

The clock input (nCP) to output (nQ) propagation delays

001aaf311

nCP input

nQ output

GND

nD input

GND

Measurement points are given in Table 9.

Fig 8.

The clock input (nCP) to output (nQ) propagation delays, clock pulse width, nD to nCP setup and hold

times and the nCP maximum frequency

001aaf312

GND

GND

nCP input

nD input

nQ output

Table 9.

Measurement points

Supply voltage

Output

Input

0.8 V to 3.6 V

0.5

× V

CC

0.5

× V

CC

≤ 3.0 ns