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74LVC1G74GT Datasheet(PDF) 4 Page - NXP Semiconductors |
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74LVC1G74GT Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 19 page 74LVC1G74_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 9 August 2007 4 of 19 NXP Semiconductors 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1 SOT902-1 CP 1 7 clock input (LOW-to-HIGH, edge-triggered) D 2 6 data input Q 3 5 complement output GND 4 4 ground (0 V) Q 5 3 true output RD 6 2 asynchronous reset-direct input (active LOW) SD 7 1 asynchronous set-direct input (active LOW) VCC 8 8 supply voltage Table 4. Function table for asynchronous operation[1] Input Output SD RD CP D Q Q L H XXH L H L XXL H L L XXH H Table 5. Function table for synchronous operation[1] Input Output SD RD CP D Qn+1 Qn+1 HH ↑ LLH HH ↑ HHL |
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