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74LVC3G04GM Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC3G04GM Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 74LVC3G04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 3 of 15 NXP Semiconductors 74LVC3G04 Triple inverter 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74LVC3G04 1A VCC 3Y 1Y 2A 3A GND 2Y 001aad954 1 2 3 4 6 5 8 7 Fig 5. Pin configuration SOT833-1 (XSON8) Fig 6. Pin configuration SOT902-1 (XQFN8) 74LVC3G04 3A 1Y VCC 2Y 2A 3Y 1A GND 001aad955 36 27 18 45 Transparent top view 74LVC3G04 001aad956 3Y 3A 1A 2A 1Y 2Y Transparent top view 3 6 1 5 7 2 terminal 1 index area Table 3. Pin description Symbol (n = 1, 2, 3) Pin Description SOT505-2, SOT765-1 and SOT833-1 SOT902-1 nA 1, 3, 6 7, 5, 2 data input nY 7, 5, 2 1, 3, 6 data output GND 4 4 ground (0 V) VCC 8 8 supply voltage |
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