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SM5921AF Datasheet(PDF) 11 Page - Nippon Precision Circuits Inc

No. de pieza SM5921AF
Descripción Electrónicos  8-channel Lip Sync Delay
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Fabricante Electrónico  NPC [Nippon Precision Circuits Inc]
Página de inicio  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5921AF Datasheet(HTML) 11 Page - Nippon Precision Circuits Inc

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SM5921A
SEIKO NPC CORPORATION —11
Intrinsic delay
The intrinsic delay is the common delay applied to each channel group, and is used to add the same delay value
to the channel group data. The default value is 0 samples. The intrinsic delay is set by the values of REG 0/H
(DIA/DOA and DIB/DOB groups) and REG 1/H (DIC/DOC and DID/DOD groups), with the values measured
in 16-sample units (333.2
µs @ fs = 48kHz).
When the TRACKT flag in REG A/H is set to HIGH, the same delay value is added to all the channel groups
(DIA/DOA, DIB/DOB, DIC/DOC, DID/DOD). See the “MCU Interface” section.
Individual delay
The individual delay is the delay applied to each channel individually, and is used to add a delay offset for each
channel data. The default value is 0 samples. The individual delay is set by the values of REG 2/H, REG 3/H,
REG 4/H, REG 5/H, REG 6/H, REG 7/H, REG 8/H, and REG 9/H, with the values measured in 1-sample units
(20.8
µs @ fs = 48kHz).
When the TRACKD flag in REG A/H is set to HIGH, the delay value set in REG 2/H (DIA/DOA left-channel)
is also applied to the DIA/DOA right-channel, DIB/DOB left-channel, and DIB/DOB right-channel data. Sim-
ilarly, the delay value set in REG 6/H (DIC/DOC left-channel) is also applied to the DIC/DOC right-channel,
DID/DOD left-channel, and DID/DOD right-channel data.
The minimum parameter settings required to apply the same delay to all channels is to set delay values in REG
0/H, REG 2/H, REG 6/H, and to set the TRACKT and TRACKD flags to HIGH. The relationship between the
intrinsic delay, individual delay, and the registers is shown in the following table.
Delay time examples
The total delay value is defined by the equation described earlier. The following table shows some examples.
Channel
Intrinsic delay
Individual delay
DIA/DOA left-channel
REG 0/H
REG 2/H
DIA/DOA right-channel
REG 3/H
DIB/DOB left-channel
REG 4/H
DIB/DOB right-channel
REG 5/H
DIC/DOC left-channel
REG 1/H
REG 6/H
DIC/DOC right-channel
REG 7/H
DID/DOD left-channel
REG 8/H
DID/DOD right-channel
REG 9/H
nSample-intrinsic + nSample-individual setting
Sampling frequency (fs)
Unit
32kHz
44.1kHz
48kHz
96kHz
192kHz
0*1
*1. Even when the set value is 0 samples, a fixed 2-sample system delay is applied.
62.5
45.4
41.7
20.8
10.4
µs
1000
31.3
22.7
20.8
10.4
5.2
ms
10000
312.5
226.8
208.3
104.2
52.1
ms
20000
625
453.5
416.7
208.3
104.2
ms
36863
1152
835.9
768
384
192
ms
65535
2048
1486.1
1365.3
682.7
341.3
ms


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