AD9913BCPZ1 datasheet(3/32 Pages) AD

No. de pieza	AD9913BCPZ1

Descripción Electrónicos	Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer

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Fabricante Electrónico	AD [Analog Devices]

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AD9913

Rev. 0 | Page 3 of 32

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, RSET = 4.64 kΩ, DAC full-scale current = 2 mA, external

reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.

Table 1.

Parameter

Conditions/Comments

Min

Typ

Max

Unit

REF_CLK INPUT CHARACTERISTICS

Frequency Range

REF_CLK Multiplier

Disabled

250

MHz

Enabled

250

MHz

REF_CLK Input Divider Frequency

Full temperature range

83

MHz

VCO Oscillation Frequency

VCO1

16

250

MHz

VCO2

100

250

MHz

PLL Lock Time

25 MHz reference clock, 10× PLL

60

μs

External Crystal Mode

25

MHz

CMOS Mode

VIH

0.9

V

VIL

0.65

V

Input Capacitance

3

pF

Input Impedance (Differential)

2.7

kΩ

Input Impedance (Single-Ended)

1.35

kΩ

Duty Cycle

45

55

%

REF_CLK Input Level

355

1000

mV p-p

DAC OUTPUT CHARACTERISTICS

Full-Scale Output Current

4.6

mA

Gain Error

−14

−6

%FS

Output Offset

+0.1

μA

Differential Nonlinearity

−0.4

+0.4

LSB

Integral Nonlinearity

−0.5

+0.5

LSB

AC Voltage Compliance Range

±400

mV

SPURIOUS-FREE DYNAMIC RANGE

Refer to Figure 6

SERIAL PORT TIMING CHARACTERISTICS

SCLK Frequency

32

MHz

SCLK Pulse Width

Low

17.5

ns

High

3.5

ns

SCLK Rise/Fall Time

2

ns

Data Setup Time to SCLK

5.5

ns

Data Hold Time to SCLK

0

ns

Data Valid Time in Read Mode

22

ns

PARALLEL PORT TIMING CHARACTERISTICS

PCLK Frequency

33

MHz

PCLK Pulse Width

Low

10

ns

High

20

ns

PCLK Rise/Fall Time

2

ns

Address/Data Setup Time to PCLK

3.0

ns

Address/Data Hold Time to PCLK

0.3

ns

Data Valid Time in Read Mode

8

ns

IO_UPDATE/PROFILE(2:0) TIMING

Setup Time to SYNC_CLK

0.5

ns

Hold Time to SYNC_CLK

1

SYNC_CLK cycles

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