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AD5329 Datasheet(PDF) 4 Page - Analog Devices |
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AD5329 Datasheet(HTML) 4 Page - Analog Devices |
4 / 4 page Two’s Complement, Dual 12-Bit DAC AD5329 REV PrC 20 DEC 99 – 4 – Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com FSYNC t 3 t 2 t 4 t 5 t 7 t 6 t 8 1 SDI 0 1 SCLK 0 1 0 Dx Dx t S ±1LSB ERROR BAND 1 V OUT 0 t 1 Dx Dx Figure 1B. Detail Timing Diagram OPERATION The AD5329 provides a 12-bit, 2’s complement, dual, voltage-output digital-to-analog converter. The first data bit of the 16-bit serial register is decoded to determine which DAC register (DAC A: A0= “0”, DAC B: A0= “1”) will be loaded with the final 12-bits of data. TABLE 3: Input Logic Control Truth Table SCLK FSYNC Register Activity L H No Shift Register Effect P L Shift One bit in from the SDA pin. L P Transfer SR data into DAC Register X L No Operation NOTE: P = positive edge, X = don't care, SR = Shift Register The data setup and data hold times in the specification table determine the data valid time requirements. The last 12 bits of the data word entered into the serial register are held when FSYNC returns high. The internal power ON reset circuit clears the serial input registers to all zeros, and sets the two DAC registers to VBZ (zero code). All digital inputs are ESD protected with a series input resistor and parallel Zener as shown in figure 7. Applies to digital input pins SCLK, SDA, FSYNC LOGIC 1K Ω Ω Figure 7. Equivalent ESD Protection Circuit OUTLINE DIMENSIONS Dimensions shown in inches and (mm) |
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