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TCA62746AFG Datasheet(PDF) 6 Page - Toshiba Semiconductor |
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TCA62746AFG Datasheet(HTML) 6 Page - Toshiba Semiconductor |
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6 / 25 page  TCA62746AFG/AFNG 2007-05-22 6 Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating *1 Unit Pow e r supply volt age VDD −0.4 to 6.0 V Output current IO 55 mA Logic i n p u t vol t a g e VIN −0.3 to VDD + 0.3 *2 V Output volt age VO −0.3 to 17 V Ope r atin g temper atu r e Topr −40 to 85 °C S t orage te mperat ure Tstg −55 to 150 °C T h er mal resist ance Rth(j-a) 94(AFG type When mounted PCB)/120(AFNG type When mounted PCB) *3 °C/W Pow e r dissip at ion PD 1.32(AFG type When mounted PCB)/1.04(AFNG type When mounted PCB) *3,4 W Note1: Voltage is ground referenced. Note2: However, do not exceed 6V. Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming) Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each degree (1°C) that the ambient temperature is exceeded (Ta = 25°C). Recommended Operating Conditions DC Items (Unless otherwise specified, Ta = −40°C to 85°C) Characteristics Symbol Test Conditions Min Typ. Max Unit Pow e r supply volt age VDD ⎯ 4.5 ⎯ 5.5 V Output voltag e w h en OFF VO (OFF) OUTn ⎯ ⎯ 16 V Ou tp ut vo lt ag e w hen O N VO (ON) OUTn 0.7 ⎯ 4 V High level logic input voltage VIH ⎯ 2.0 ⎯ VDD V Low level logic input voltage VIL ⎯ GND ⎯ 0.8 V High level SOUT output current IOH VDD = 5 V ⎯ ⎯ −1 mA Low level SOUT output current IOL VDD = 5 V ⎯ ⎯ 1 mA Const ant cu rrent out put IO OUTn 2 ⎯ 50 mA AC Items (Unless otherwise specified, VDD = 4.5 to 5.5 V, Ta = −40°C to 85°C) Characteristics Symbol Test Circuits Test Conditions Min Typ. Max Unit Serial data transfer frequency fSCK 7 ⎯ ⎯ ⎯ 25 MHz Clock pulse w i d t h twSCK 7 SCK = “H” or “L” 20 ⎯ ⎯ ns Lat ch p u l se w i d t h twSLAT 7 SLAT = “H” 20 ⎯ ⎯ ns twOE1 7 OE = “H” or “L” ,REXT = 500 Ω 100 ⎯ ⎯ ns E n ab le pulse w i d t h twOE2 ⎯ When error is detected *1 2 ⎯ ⎯ µs tHOLD1 7 ⎯ 5 ⎯ ⎯ ns tHOLD2 7 ⎯ 5 ⎯ ⎯ ns tHOLD3 7 ⎯ 10 ⎯ ⎯ ns Hol d ti me tHOLD4 7 ⎯ 10 ⎯ ⎯ ns tSETUP1 7 ⎯ 5 ⎯ ⎯ ns tSETUP2 7 ⎯ 5 ⎯ ⎯ ns tSETUP3 7 ⎯ 10 ⎯ ⎯ ns Set u p tim e tSETUP4 7 ⎯ 10 ⎯ ⎯ ns Maximum clo ck rise time tr 7 *2 ⎯ ⎯ 500 ns Maximum clo ck fall time tf 7 *2 ⎯ ⎯ 500 ns Note1: Please refer to page 16 for details of the error detection. Note2: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform, it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when designing your application. |
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