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DLX1414 Datasheet(PDF) 4 Page - OSRAM GmbH |
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DLX1414 Datasheet(HTML) 4 Page - OSRAM GmbH |
4 / 4 page 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA Appnote 15 www.infineon.com/opto • 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany www.osram-os.com • +49-941-202-7178 4 May 31, 2000-12 Figure 8. 16-digit parallel I/O Figure 8 illustrates a 16-character display with an 8080 system using the 8255 programmable peripheral interface I/O device. The following program will display a simple 16 character mes- sage using this interface. Program for 16-Character Message INT: MVI A,80H OUT CON- TROLMVI B,00H ;CONTROL DATA MODE 0 ;LOAD CONTROL REGISTER ;SET COUNTER =0 DISP: LXI H, TABLE ;SET TABLE ADDRESS DISP1: MOV A,M OUT PORTA MOV A, B CALL DSPWT INX H INR B MVI A, 10H CMP B JNZ DISP1 HALT ;MOVE TABLE DATA TO ACCUMULATOR ;LOAD DATA PORT ;LOAD ADDRESS AND CONTROL ;INCREMENT TABLE ADDRESS ;INCREMENT COUNTER ;SET # OF DIGITS ;16 CHARACTERS ? ;END OF PROGRAM DSPWT: ORI F0H OUT PORTB ANI 7FH OUT PORTB ORI F0H OUT PORTB RET ;SET CONTROL BITS OFF ;LOAD CONTROL ;SET WRITE BIT ON ;LOAD WRITE ;SET WRITE BIT OFF ;LOAD CONTROL TABLE: DL DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB ;0C3H ;0C9H ;0D4H ;0D3H ;0C1H ;0D4H ;0CEH ;0C1H ;0C6H ;0A0H ;0D3H ;0D4H ;0C8H ;0C7H ;0C9H ;0CCH 8255 Display Po rt A 0 – 6 Port B A B 3 2 1 0 Vcc GND Data Control 8080 P System A0 A1 A2 A3 0 1 2 3 4 5 6 7 7442 D15 D0 WR Display WR Display WR Display WR C D D0 – D6 WR 2 I/O or Memory Mapped Addressing Some designers may wish to avoid the additional cost of a par- allel l/O in their system. Structuring the addressing architecture for the DLX1414 to look like a set of peripheral or output devices (I/O mapped) or RAMs and ROMs (memory mapped), is very easy. Figure 9 shows the simplicity of interfacing to microprocessors, such as 8080, Z80 and 6502 as examples. The interface with the 6800 microprocessor in Figure 10 illus- trates the need for designers to check the timing requirements of the DLX1414 and the LP. The typical data output hold time is only 30 ns for DBE=02 timing; two inverters in the DBE line are added to increase the data output hold time for compatibility with the 50 ns minimum spec of the DLX1414. Figure 9. Mapped interface Figure 10. Gating the write pulse Conclusion Although other manufacturers’ products are used in examples, this application note does not imply specific endorsement, or recom- mendation or warranty of other manufacturer’s products by Infineon / OSRAM. The interface schemes shown demonstrate the simplicity of using the DLX1414 with microprocessors. The slight differences encountered with different microprocessors to interface with the DLX1414 are similar to those encountered when using dif- ferent RAMs The techniques used in the examples were shown for their generality. The user will undoubtedly invent other schemes to optimize his particular system to its requirements. Address Dis play Select Decoder Optional Buffers Reset Int Hold Wait Display Display Display Display 8080 Z80 6502 D15 D0 OSC A0 A1 A2 A3 Data 0-6 WR Address Data Control Data 0 1 2 3 A B C D Address DBE Decoder Data Address H1 H2 01 02 Clock Driver 6800 BA VMA R/W CE CE Reset NMI Halt IRQ TSC A0, A1 D0–D7 Display Display Display Display Data |
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Descripción similar - DLX1414 |
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