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AD5762R Datasheet(PDF) 7 Page - Analog Devices |
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AD5762R Datasheet(HTML) 7 Page - Analog Devices |
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7 / 33 page  Preliminary Technical Data AD5762R Rev. PrA | Page 7 of 33 TIMING CHARACTERISTICS AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external; DVCC = 2.7 V to 5.25 V, RLOAD = 10 kΩ, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t54 13 ns min 24th SCLK falling edge to SYNC rising edge t6 40 ns min Minimum SYNC high time t7 2 ns min Data setup time t8 5 ns min Data hold time t9 1.4 µs min SYNC rising edge to LDAC falling edge (all DACs updated) 400 ns min SYNC rising edge to LDAC falling edge (single DAC updated) t10 10 ns min LDAC pulse width low t11 500 ns max LDAC falling edge to DAC output response time t12 10 µs max DAC output settling time t13 10 ns min CLR pulse width low t14 2 µs max CLR pulse activation time t155, 6 25 ns max SCLK rising edge to SDO valid t16 13 ns min SYNC rising edge to SCLK falling edge t17 2 µs min SYNC rising edge to DAC output response time (LDAC = 0) t18 170 ns min LDAC falling edge to SYNC rising edge 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Standalone mode only. 5 Measured with the load circuit of Figure 5. 6 Daisy-chain mode only. |
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Descripción similar - AD5762R |
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