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TLC070IDGNRG4 Datasheet(PDF) 7 Page - Texas Instruments |
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TLC070IDGNRG4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 50 page TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA FAMILY OF WIDEBANDWIDTH HIGHOUTPUT DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 7 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA† MIN TYP MAX UNIT SR+ Positive slew rate at unity gain VO(PP) = 0.8 V, CL = 50 pF, 25 °C 10 16 V/ s SR+ Positive slew rate at unity gain VO(PP) = 0.8 V, RL = 10 kΩ CL = 50 pF, Full range 9.5 V/ µs SR− Negative slew rate at unity gain VO(PP) = 0.8 V, CL = 50 pF, 25 °C 12.5 19 V/ s SR− Negative slew rate at unity gain VO(PP) = 0.8 V, RL = 10 kΩ CL = 50 pF, Full range 10 V/ µs Vn Equivalent input noise voltage f = 100 Hz 25 °C 12 nV/ √Hz Vn Equivalent input noise voltage f = 1 kHz 25 °C 7 nV/ √Hz In Equivalent input noise current f = 1 kHz 25 °C 0.6 fA / √Hz VO(PP) = 3 V, AV = 1 0.002% THD + N Total harmonic distortion plus noise VO(PP) = 3 V, RL = 10 kΩ and 250 Ω, f = 1 kHz AV = 10 25 °C 0.012% THD + N Total harmonic distortion plus noise RL = 10 kΩ and 250 Ω, f = 1 kHz AV = 100 25 C 0.085% t(on) Amplifier turn-on time‡ RL = 10 kΩ 25 °C 0.15 µs t(off) Amplifier turn-off time‡ RL = 10 kΩ 25 °C 1.3 µs Gain-bandwidth product f = 10 kHz, RL = 10 kΩ 25 °C 10 MHz V(STEP)PP = 1 V, AV = −1, 0.1% 0.18 ts Settling time AV = −1, CL = 10 pF, RL = 10 kΩ 0.01% 25 °C 0.39 s ts Settling time V(STEP)PP = 1 V, AV = −1, 0.1% 25 °C 0.18 µs AV = −1, CL = 47 pF, RL = 10 kΩ 0.01% 0.39 φm Phase margin RL = 10 kΩ, CL = 50 pF 25 °C 32 ° φm Phase margin RL = 10 kΩ, CL = 0 pF 25 °C 40 ° Gain margin RL = 10 kΩ, CL = 50 pF 25 °C 2.2 dB Gain margin RL = 10 kΩ, CL = 0 pF 25 °C 3.3 dB † Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. ‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. |
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