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ADS6144 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS6144 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 68 page www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) ADS6145, ADS6144 ADS6143, ADS6142 SLWS198A – JULY 2007 – REVISED OCTOBER 2007 Typical values are at 25 °C, min and max values are across the full temperature range T MIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), I O = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet. ADS6145 ADS6144 ADS6143 ADS6142 FS = 125 MSPS FS = 105 MSPS FS = 80 MSPS FS = 65 MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Aperture ta 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns delay Aperture tj 150 150 150 150 fs rms jitter From global power 15 50 15 50 15 50 15 50 µs down Wake-up time From standby 15 50 15 50 15 50 15 50 µs (to valid From output CMOS 100 200 100 200 100 200 100 200 ns data) buffer LVDS 200 500 200 500 200 500 200 500 ns disable clock Latency 9 9 9 9 cycles DDR LVDS MODE(4), DRVDD = 3.3 V Data valid (6) to Data setup tsu zero-cross of 1.7 2.3 2.5 3.1 3.9 4.5 5.4 6.0 ns time(5) CLKOUTP Zero-cross of Data hold th CLKOUTP to data 0.7 1.7 0.7 1.7 0.7 1.7 0.7 1.7 ns time(5) becoming invalid(6) Input clock rising edge Clock zero-cross to output tPDI propagation 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 ns clock rising edge delay zero-cross Duty cycle of LVDS bit differential clock, clock duty (CLKOUTP- 40% 47% 55% 40% 47% 55% 40% 47% 55% 40% 47% 55% cycle CLKOUTM), 10 ≤ Fs ≤ 125 MSPS Rise time measured from –50 mV to 50 Data rise mV, tr time, Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps tf Data fall from 50 mV to –50 time mV, 1 ≤ Fs ≤ 125 MSPS Rise time measured from –50 mV to 50 tCLKRI Output clock mV, SE rise time, Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps tCLKFA Output clock from 50 mV to –50 LL fall time mV, 1 ≤ Fs ≤ 125 MSPS PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.3 V, default output buffer drive strength (7) Data setup Data valid(8) to 50% of tsu 2.9 4.4 3.6 5.1 5.1 6.6 6.5 8.0 ns time(5) CLKOUT rising edge 50% of CLKOUT rising Data hold th edge to data becoming 1.3 2.7 2.1 3.5 3.6 5.0 5.1 6.5 ns time(5) invalid(8) (1) Timing parameters are specified by design and characterization and not tested in production. (2) CL is the Effective external single-ended load capacitance between each output pin and ground. (3) IO Refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. (4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. (5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to a logic high of +100 mV and logic low of –100 mV. (7) For DRVDD < 2.2 V, it is recommended to use an external clock for data capture and NOT the device output clock signal (CLKOUT). See Parallel CMOS interface in the application section. (8) Data valid refers to a logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V). Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS6145, ADS6144 ADS6143, ADS6142 |
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