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ADS62P44 Datasheet(PDF) 5 Page - Texas Instruments |
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ADS62P44 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 67 page ADS62P45, ADS62P44 ADS62P43, ADS62P42 REV1P0 SEP 2007 5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com www.ti.com RECOMMENDED OPERATING CONDITIONS PARAMETER MIN TYP MAX UNIT SUPPLIES AVDD Analog supply voltage 3.0 3.3 3.6 V CMOS interface 1.65 1.8 to 3.3 3.6 V DRVDD Digital supply voltage LVDS interface 3.0 3.3 3.6 V ANALOG INPUTS Differential input voltage range 2 VPP Input common-mode voltage 1.5 +/- 0.1 V Voltage applied on CM in external reference mode 1.5 ± 0.05 V CLOCK INPUT ADS62P45 1 125 MSPS ADS62P44 1 105 MSPS ADS62P43 1 80 MSPS Input clock sample rate, Fs ADS62P42 1 65 MSPS Sine wave, ac-coupled 0.3 3.0 V pp LVPECL, ac-coupled 1.6 V pp LVDS, ac-coupled 0.7 V pp Input Clock amplitude differential (VCLKP-VCLKM) LVCMOS, single-ended, ac-coupled 3.3 V Input clock duty cycle 35 % 50 % 65 % DIGITAL OUTPUTS For CLOAD <= 5 pF and DRVDD >= 2.2V Default strength For CLOAD > 5 pF and DRVDD > 2.2V Maximum strength Output buffer drive strength For DRVDD < 2.2V Maximum strength CMOS interface 5 pF LVDS interface, without internal termination 5 pF CLOAD, Maximum external load capacitance from each output pin to DRGND LVDS interface, with 100 Ω internal termination 10 pF RLOAD, Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω Operating free-air temperature, TA -40 85 °C |
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