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SST89E58RD2-33-I-NJE1 Datasheet(PDF) 64 Page - Silicon Storage Technology, Inc |
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SST89E58RD2-33-I-NJE1 Datasheet(HTML) 64 Page - Silicon Storage Technology, Inc |
64 / 81 page 64 Data Sheet FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD ©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 TABLE 14-2: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method NEND1 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T14-2.0 1255 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 14-3: AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 14-8 and 14-10 T14-3.0 1255 TABLE 14-4: Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter Power-up to Read Operation 100 µs TPU-WRITE1 Power-up to Write Operation 100 µs T14-4.0 1255 TABLE 14-5: Pin Impedance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. I/O Pin Capacitance VI/O = 0V 15 pF CIN1 Input Capacitance VIN = 0V 12 pF LPIN2 2. Refer to PCI spec. Pin Inductance 20 nH T14-5.0 1255 |
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