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SST89V52RD2-33-I-TQIF2 Datasheet(PDF) 61 Page - Silicon Storage Technology, Inc |
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SST89V52RD2-33-I-TQIF2 Datasheet(HTML) 61 Page - Silicon Storage Technology, Inc |
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61 / 81 page  Data Sheet FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD 61 ©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 12.0 POWER-SAVING MODES The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are idle and power-down, see Table 12-1. 12.1 Idle Mode Idle mode is entered setting the IDL bit in the PCON regis- ter. In idle mode, the program counter (PC) is stopped. The system clock continues to run and all interrupts and periph- erals remain active. The on-chip RAM and the special func- tion registers hold their data during this mode. The device exits idle mode through either a system inter- rupt or a hardware reset. Exiting idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. A hardware reset starts the device similar to a power-on reset. 12.2 Power-down Mode The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents are retained during power- down, the minimum VDD level is 2.0V. The device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits power-down. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon interrupt signal being restored to logic VIH, the first instruc- tion of the interrupt service routine will execute. A hardware reset starts the device similar to power-on reset. To exit properly out of power-down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). TABLE 12-1: Power Saving Modes Mode Initiated by State of MCU Exited by Idle Mode Software (Set IDL bit in PCON) MOV PCON, #01H; CLK is running. Interrupts, serial port and tim- ers/counters are active. Pro- gram Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged. Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits idle mode, after the ISR RETI instruction, program resumes execu- tion beginning at the instruction follow- ing the one that invoked idle mode. A user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. Power-down Mode Software (Set PD bit in PCON) MOV PCON, #02H; CLK is stopped. On-chip SRAM and SFR data is main- tained. ALE and PSEN# sig- nals at a LOW level during power -down. External Inter- rupts are only active for level sensitive interrupts, if enabled. Enabled external level sensitive inter- rupt or hardware reset. Start of inter- rupt clears PD bit and exits power- down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. A user could consider placing two or three NOP instructions after the instruction that invokes power-down mode to eliminate any problems. A hardware reset restarts the device sim- ilar to a power-on reset. T12-1.0 1255 |
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