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SST89E58RD2-33-C-NJF2 Datasheet(PDF) 67 Page - Silicon Storage Technology, Inc |
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SST89E58RD2-33-C-NJF2 Datasheet(HTML) 67 Page - Silicon Storage Technology, Inc |
67 / 81 page Data Sheet FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD 67 ©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 TABLE 14-7: DC Electrical Characteristics for SST89V5xRD2/RD TA = -40°C to +85°C; VDD = 2.7-3.6V; VSS = 0V Symbol Parameter Test Conditions Min Max Units VIL Input Low Voltage 2.7 < VDD < 3.6 -0.5 0.7 V VIH Input High Voltage 2.7 < VDD < 3.6 0.2VDD + 0.9 VDD + 0.5 V VIH1 Input High Voltage (XTAL1, RST) 2.7 < VDD < 3.6 0.7VDD VDD + 0.5 V VOL Output Low Voltage (Ports 1.5, 1.6, 1.7) VDD = 2.7V IOL = 16mA 1.0 V VOL Output Low Voltage (Ports 1, 2, 3)1 VDD = 2.7V IOL = 100µA2 0.3 V IOL = 1.6mA2 0.45 V IOL = 3.5mA2 1.0 V VOL1 Output Low Voltage (Port 0, ALE, PSEN#)1,3 VDD = 2.7V IOL = 200µA2 0.3 V IOL = 3.2mA2 0.45 V VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 VDD = 2.7V IOH = -10µA VDD - 0.3 V IOH = -30µA VDD - 0.7 V IOH = -60µA VDD - 1.5 V VOH1 Output High Voltage (Port 0 in External Bus Mode)4 VDD = 2.7V IOH = -200µA VDD - 0.3 V IOH = -3.2mA VDD - 0.7 V VBOD Brown-out Detection Voltage 2.35 2.55 V IIL Logical 0 Input Current (Ports 1, 2, 3) VIN = 0.4V -75 µA ITL Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 VIN = 2V -650 µA ILI Input Leakage Current (Port 0) 0.45 < VIN < VDD-0.3 ±10 µA RRST RST Pull-down Resistor 225 K Ω CIO Pin Capacitance6 @ 1 MHz, 25°C 15 pF IDD Power Supply Current IAP Mode @ 33 MHz 47 mA Active Mode @ 33 MHz 30 mA Idle Mode @ 33 MHz 21 mA Power-down Mode TA = 0°C to +70°C 45 µA TA = -40°C to +85°C 55 µA T14-7.1 1255 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA Maximum IOL per 8-bit port: 26mA Maximum IOL total for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF. |
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