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SST89E54RD2-40-I-NJ Datasheet(PDF) 38 Page - Silicon Storage Technology, Inc

No. de pieza SST89E54RD2-40-I-NJ
Descripción Electrónicos  FlashFlex51 MCU
Download  81 Pages
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Fabricante Electrónico  SST [Silicon Storage Technology, Inc]
Página de inicio  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST89E54RD2-40-I-NJ Datasheet(HTML) 38 Page - Silicon Storage Technology, Inc

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Data Sheet
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
©2006 Silicon Storage Technology, Inc.
S71255-05-000
5/06
Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.
5.0 TIMERS/COUNTERS
5.1 Timers
The device has three 16-bit registers that can be used as
either timers or event counters. The three timers/counters
are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2).
Each is designated a pair of 8-bit registers in the SFRs.
The pair consists of a most significant (high) byte and least
significant (low) byte. The respective registers are TL0,
TH0, TL1, TH1, TL2, and TH2.
5.2 Timer Set-up
Refer to Table 3-8 for TMOD, TCON, and T2CON registers
regarding timers T0, T1, and T2. The following tables pro-
vide TMOD values to be used to set up Timers T0, T1, and
T2.
Except for the baud rate generator mode, the values given
for T2CON do not include the setting of the TR2 bit. There-
fore, bit TR2 must be set separately to turn the timer on.
TABLE
4-2: IAP Commands1
Operation
SFCM [6:0]2
SFDT [7:0]
SFAH [7:0]
SFAL [7:0]
Chip-Erase3
01H
55H
X4
X
Block-Erase
0DH
55H
AH5
X
Sector-Erase
0BH
X
AH
AL6
Byte-Program
0EH
DI7
AH
AL
Byte-Verify (Read)8
0CH
DO7
AH
AL
Prog-SB19
0FH
AAH
X
X
Prog-SB29
03H
AAH
X
X
Prog-SB39
05H
AAH
X
X
Prog-SC09
09H
AAH
5AH
X
Prog-SC19
09H
AAH
AAH
X
Enable-Clock-Double9
08H
AAH
55H
X
T4-2.0 1255
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
SFCM[7] = 1: Interrupt enable for flash operation completion
0: polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. X can be VIL or VIH, but no other value.
5. AH = Address high order byte
6. AL = Address low order byte
7. DI = Data Input, DO = Data Output, all other values are in hex.
8. SFAH[7:5] = 111b selects Block 1, SFAH[7] = 0b selects Block 0
9. Instruction must be located in Block 1 or external code memory.
TABLE
5-1: Timer/Counter 0
Mode
Function
TMOD
Internal
Control1
1. The Timer is turned ON/OFF by setting/clearing
bit TR0 in the software.
External
Control2
2. The Timer is turned ON/OFF by the 1 to 0 transition
on INT0# (P3.2) when TR0 = 1 (hardware control).
Used as
Timer
0
13-bit Timer
00H
08H
1
16-bit Timer
01H
09H
2
8-bit Auto-Reload
02H
0AH
3
Two 8-bit Timers
03H
0BH
Used as
Counter
0
13-bit Timer
04H
0CH
1
16-bit Timer
05H
0DH
2
8-bit Auto-Reload
06H
0EH
3
Two 8-bit Timers
07H
0FH
T5-1.0 1255


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