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SST89E58RD2-40-C-NJE Datasheet(PDF) 16 Page - Silicon Storage Technology, Inc |
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SST89E58RD2-40-C-NJE Datasheet(HTML) 16 Page - Silicon Storage Technology, Inc |
16 / 81 page 16 Data Sheet FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD ©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 3.5 Dual Data Pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-5) FIGURE 3-5: Dual Data Pointer Organization 3.6 Special Function Registers Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function regis- ters (SFRs) located in the SFR memory map shown in Table 3-4. Individual descriptions of each SFR are provided and reset values indicated in Tables 3-5 to 3-9. TABLE 3-4: FlashFlex51 SFR Memory Map 8 BYTES F8H IP11 1. Bit addressable SFRs CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H FFH F0H B1 IP1H F7H E8H IEA1 CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L EFH E0H ACC1 E7H D8H CCON1 CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 DFH D0H PSW1 SPCR D7H C8H T2CON1 T2MOD RCAP2L RCAP2H TL2 TH2 CFH C0H WDTC1 C7H B8H IP1 SADEN BFH B0H P31 SFCF SFCM SFAL SFAH SFDT SFST IPH B7H A8H IE1 SADDR SPSR XICON AFH A0H P21 AUXR1 P4 A7H 98H SCON1 SBUF 9FH 90H P11 97H 88H TCON1 TMOD TL0 TL1 TH0 TH1 AUXR 8FH 80H P01 SP DPL DPH WDTD SPDR PCON 87H T3-4.0 1255 DPL 82H DPS = 0 → DPTR0 DPS = 1 → DPTR1 External Data Memory DPS 1255 F06.0 DPH 83H DPTR0 DPTR1 AUXR1 / bit0 |
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