©1988 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74AC377, 74ACT377 Rev. 1.6.1

January 2008

74AC377, 74ACT377

Octal D-Type Flip-Flop with Clock Enable

Features

applications

General Description

The AC/ACT377 has eight edge-triggered, D-type flip-

flops with individual D inputs and Q outputs. The com-

mon buffered Clock (CP) input loads all flip-flops simulta-

neously, when the Clock Enable (CE) is LOW.

The register is fully edge-triggered. The state of each D

input, one setup time before the LOW-to-HIGH clock

transition, is transferred to the corresponding flip-flop's Q

output. The CE input must be stable only one setup time

prior to the LOW-to-HIGH clock transition for predictable

operation.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number

Package Description

74AC377SC

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74AC377SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC377MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74ACT377SC

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74ACT377SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT377MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74ACT377PC

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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