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S-1111B24MC-NYJTFG Datasheet(PDF) 14 Page - Seiko Instruments Inc |
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S-1111B24MC-NYJTFG Datasheet(HTML) 14 Page - Seiko Instruments Inc |
14 / 25 page HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR S-1111/1121 Series Rev.4.1_00 Seiko Instruments Inc. 14 Operation 1. Basic operation Figure 11 shows the block diagram of the S-1111/1121 Series. The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance- divided by feedback resistors Rs and Rf. It supplies the output transistor with the gate voltage necessary to ensure a certain output voltage free of any fluctuations of input voltage and temperature. Reference voltage circuit VOUT *1 *1. Parasitic diode VSS VIN Rs Rf Error amplifier Current supply Vref − + Vfb Figure 11 2. Output transistor The S-1111/1121 Series uses a low on-resistance P-channel MOS FET as the output transistor. Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to inverse current flowing from VOUT pin through a parasitic diode to VIN pin. |
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