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S-1132B43-I6T2G Datasheet(PDF) 14 Page - Seiko Instruments Inc |
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S-1132B43-I6T2G Datasheet(HTML) 14 Page - Seiko Instruments Inc |
14 / 35 page HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR S-1132 Series Rev.3.2_00 14 Seiko Instruments Inc. 3. Shutdown pin (ON/OFF pin) This pin starts and stops the regulator. When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-in P-channel MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially reduce the current consumption. The VOUT pin becomes the VSS level due to the internally divided resistance of several hundreds k Ω between the VOUT pin and VSS pin. The structure of the ON/OFF pin is as shown in Figure 14. Since the ON/OFF pin is neither pulled down nor pulled up internally, do not use it in the floating state. In addition, note that the current consumption increases if a voltage of 0.3 V to VIN – 0.3 V is applied to the ON/OFF pin. When the ON/OFF pin is not used, connect it to the VSS pin if the logic type is “A” and to the VIN pin if it is “B”. Table 7 Logic Type ON/OFF Pin Internal Circuits VOUT Pin Voltage Current Consumption A “L”: Power on Operating Set value ISS1 A “H”: Power off Stopped VSS level ISS2 B “L”: Power off Stopped VSS level ISS2 B “H”: Power on Operating Set value ISS1 VSS ON/OFF VIN Figure 14 |
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