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ADUM1420BRWZ-RL Datasheet(PDF) 10 Page - Analog Devices |
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ADUM1420BRWZ-RL Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page ADuM1420 Rev. A | Page 10 of 12 POWER-UP/POWER-DOWN CONSIDERATIONS Given that the ADuM1420 has separate supplies on either side of the isolation barrier for each channel, the power-up/power- down characteristics relative to each supply voltage need to be considered individually. As shown in Table 7, when VDD1 input power is off, the ADuM1420 outputs take on a default low logic state. As the VDD1 supply is increased/decreased, the output of each channel transitions from/to a logic low to/from the state matching its respective input (see Figure 13 and Figure 14). OUTPUT DATA 2.5 (TYP) VDD1 Figure 13. VDD1 Power-Up/Power-Down Characteristics, Input Data = High OUTPUT DATA VDD1 Figure 14. VDD1 Power-Up/Power-Down Characteristics, Input Data = Low When VDD1 crosses the threshold for activating the refresh function (approximately 2.5 V), there can be a delay of up to 2 μs before the output is updated to the correct state, depending on the timing of the next refresh pulse. When VDD1 is reduced from an on state to below the 2.0 V threshold, there can be a delay of up to 5 μs before the output takes on its default low state. In addition, during power-up/power-down, there is a range of VDD1 values within which erroneous outputs can occur if the input data either is a logic high or is in transition between logic states. This range is between 2.5 V and 2.7 V. The recommended practice is to set all the input logic levels to low during power-up/ power-down. |
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