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ADUM2201ARWZ Datasheet(PDF) 5 Page - Analog Devices |
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ADUM2201ARWZ Datasheet(HTML) 5 Page - Analog Devices |
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5 / 20 page  ADuM2200/ADuM2201 Rev. 0 | Page 5 of 20 ELECTRICAL CHARACTERISTICS—3 V OPERATION1 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent IDDI (Q) 0.3 0.5 mA Output Supply Current, per Channel, Quiescent IDDO (Q) 0.3 0.5 mA ADuM2200, Total Supply Current, Two Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.8 1.3 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2 (Q) 0.7 1.0 mA DC to 1 MHz logic signal frequency 10 Mbps (BR Grade Only) VDD1 Supply Current IDD1 (10) 2.0 3.2 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 1.1 1.7 mA 5 MHz logic signal frequency ADuM2201, Total Supply Current, Two Channels2 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 0.7 1.3 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2 (Q) 0.8 1.6 mA DC to 1 MHz logic signal frequency 10 Mbps (BR Grade Only) VDD1 Supply Current IDD1 (10) 1.5 2.1 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 1.9 2.4 mA 5 MHz logic signal frequency For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ VDD1 or VDD2 Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V Logic High Output Voltages VOAH (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 μA, VIx = VIxH VOBH (VDD1 or VDD2) − 0.5 2.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL 0.0 0.1 V IOx = 20 μA, VIx = VIxL VOBL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM220xAR Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 20 150 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 100 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching7 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) tR/tF 10 ns CL = 15 pF, CMOS signal levels ADuM220xBR Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 20 60 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH −tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels |
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