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ADC121S051CISD Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza ADC121S051CISD
Descripción Electrónicos  Single Channel, 200 to 500ksps, 12-Bit A/D Converter
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC121S051CISD Datasheet(HTML) 11 Page - National Semiconductor (TI)

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Applications Information
1.0 ADC121S051 OPERATION
The ADC121S051 is a successive-approximation analog-to-
digital converters designed around a charge-redistribution
digital-to-analog converter core. Simplified schematics of the
ADC121S051 in both track and hold modes are shown in
Figure 3 and Figure 4, respectively. In Figure 3, the device is
in track mode: switch SW1 connects the sampling capacitor
to the input, and SW2 balances the comparator inputs. The
device is in this state until CS is brought low, at which point
the device moves to the hold mode.
Figure 4 shows the device in hold mode: switch SW1 con-
nects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge from the
sampling capacitor until the comparator is balanced. When
the comparator is balanced, the digital word supplied to the
DAC is the digital representation of the analog input voltage.
The device moves from hold mode to track mode on the 13th
rising edge of SCLK.
2.0 USING THE ADC121S051
The serial interface timing diagram for the ADC121S051 is
shown in Figure 2. CS is chip select, which initiates conver-
sions on the ADC121S051 and frames the serial data trans-
fers. SCLK (serial clock) controls both the conversion pro-
cess and the timing of serial data. SDATA is the serial data
out pin, where a conversion result is found as a serial data
stream.
Basic operation of the ADC121S051 begins with CS going
low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled
with reference to the falling edge of CS; for example, "the
third falling edge of SCLK" shall refer to the third falling edge
of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE,
and the converter moves from track mode to hold mode. The
input signal is sampled and held for conversion on the falling
edge of CS. The converter moves from hold mode to track
mode on the 13th rising edge of SCLK (see Figure 2). The
SDATA pin will be placed back into TRI-STATE after the 16th
falling edge of SCLK, or at the rising edge of CS, whichever
occurs first. After a conversion is completed, the quiet time
(t
QUIET) must be satisfied before bringing CS low again to
begin another conversion.
Sixteen SCLK cycles are required to read a complete
sample from the ADC121S051. The sample bits (including
leading zeroes) are clocked out on falling edges of SCLK,
and are intended to be clocked in by a receiver on subse-
quent falling edges of SCLK. The ADC121S051 will produce
three leading zero bits on SDATA, followed by twelve data
bits, most significant first.
If CS goes low before the rising edge of SCLK, an additional
(fourth) zero bit may be captured by the next falling edge of
SCLK.
20144609
FIGURE 3. ADC121S051 in Track Mode
20144610
FIGURE 4. ADC121S051 in Hold Mode
www.national.com
11


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