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ADC12132CIMSA Datasheet(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza ADC12132CIMSA
Descripción Electrónicos  Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12132CIMSA Datasheet(HTML) 9 Page - National Semiconductor (TI)

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AC Electrical Characteristics
The following specifications apply for (V
+ =V
A+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V
common-mode voltage) or (V
+ =V
A+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-
mode voltage), V
REF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, VREF− and VREF+
≤ 25Ω,f
CK
=f
SK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ =TMIN to TMAX; all
other limits T
A =TJ = 25˚C. (Note 17) (Continued)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
t
HPU
Hardware Power-Up Time, Time from PD
Falling Edge to EOC Rising Edge
500
700
µs (max)
t
SPU
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to EOC
Rising Edge
500
700
µs (max)
t
ACC
Access Time Delay from CS Falling Edge
to DO Data Valid
25
60
ns (max)
t
SET-UP
Set-Up Time of CS Falling Edge to Serial
Data Clock Rising Edge
50
ns (min)
t
DELAY
Delay from SCLK Falling Edge to CS
Falling Edge
0
5
ns (min)
t
1H,t0H
Delay from CS Rising Edge to DO
TRI-STATE
R
L = 3k, CL = 100 pF
70
100
ns (max)
t
HDI
DI Hold Time from Serial Data Clock
Rising Edge
5
15
ns (max)
t
SDI
DI Set-Up Time from Serial Data Clock
Rising Edge
5
10
ns (min)
t
HDO
DO Hold Time from Serial Data Clock
Falling Edge
R
L = 3k, CL = 100 pF
35
65
5
ns (max)
ns (min)
t
DDO
Delay from Serial Data Clock Falling Edge
to DO Data Valid
50
90
ns (max)
t
RDO
DO Rise Time, TRI-STATE to High DO
Rise Time, Low to High
R
L = 3k, CL = 100 pF
10
10
40
40
ns (max)
ns (max)
t
FDO
DO Fall Time, TRI-STATE to Low DO Fall
Time, High to Low
R
L = 3k, CL = 100 pF
15
15
40
40
ns (max)
ns (max)
t
CD
Delay from CS Falling Edge to DOR
Falling Edge
45
80
ns (max)
t
SD
Delay from Serial Data Clock Falling Edge
to DOR Rising Edge
45
80
ns (max)
C
IN
Capacitance of Logic Inputs
20
pF
C
OUT
Capacitance of Logic Outputs
20
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+orVD+), the current at that pin should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD =(TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJmax = 150˚C.
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 k
Ω resistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55
VDC to ensure accurate conversions.
www.national.com
9


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