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L6223 Datasheet(PDF) 5 Page - STMicroelectronics |
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L6223 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 33 page ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Test conditions Min Typ Max Unit SWITCHING TIMING t2, t4 Fall/Rise Time (IN1, 2, 3, 4) R(load) =39 Ω (Fig. 5) Pure Resistive Load to VS 250 ns t1, t3 Input-Output Delay (IN1, 2, 3, 4) R(load) =39 Ω (Fig. 5) Pure Resistive Load to VS 700 ns tdPWM Close Loop PWM Control Delay (Fig. 4) Note 1 1 µs PROGRAMMING TIMING t1 Loading Time (Fig. 6) 1.7 µs t2 Protection Time (Fig. 6) Note 2 0.2 µs t3 Data Set-up (Fig. 6) 0 ns t4 Data Hold (Fig. 6) 1.6 µs t5 Setting Time (Fig. 6) 200 ns Note 1) Upper DMOS turn ON delay when the signal is applied at the input comparator (point A in Fig. 4). Note 2) Internal clock pulse is generated only if IN1...IN4 stay Low for almost 0.2 µs. This delay avoids undesirable programmings. Figure 1: Output leakage IOL Test Circuit Figure 2a: Source Output DMOS RDS(ON) Test Circuit L6223 5/33 |
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