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LM75BIMMX-3 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LM75BIMMX-3 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 18 page 1.0 Functional Description (Continued) above the nominal 1.7V power up threshold, the internal registers are reset to the power up default values listed above. 1.3 I 2C BUS INTERFACE The LM75 operates as a slave on the I 2C bus, so the SCL line is an input (no clock is generated by the LM75) and the SDA line is a bi-directional serial data path. According to I 2C bus specifications, the LM75 has a 7-bit slave address. The four most significant bits of the slave address are hard wired inside the LM75 and are “1001”. The three least significant bits of the address are assigned to pins A2–A0, and are set by connecting these pins to ground for a low, (0); or to +V S for a high, (1). Therefore, the complete slave address is: 1 0 0 1 A2 A1 A0 MSB LSB 01265807 Note 14: These interrupt mode resets of O.S. occur only when LM75 is read or placed in shutdown. Otherwise, O.S. would remain active indefinitely for any event. FIGURE 4. O.S. Output Temperature Response Diagram www.national.com 8 |
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Descripción similar - LM75BIMMX-3 |
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