CAT9555WI datasheet(9/17 Pages) CATALYST

No. de pieza	CAT9555WI

Descripción Electrónicos	16-bit I2C and SMBus I/O Port with Interrupt

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Fabricante Electrónico	CATALYST [Catalyst Semiconductor]

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CAT9555

9

Doc. No. MD-9003, Rev. G

Characteristics subject to change without notice

Figure 5. Start/Stop Timing

FUNCTIONAL DESCRIPTION

The CAT9555 general purpose input/output (GPIO)

peripheral provides up to sixteen I/O ports, controlled

through an I2C compatible serial interface

The CAT9555 supports the I2C Bus data transmission

protocol. This Inter-Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter

and any device receiving data to be a receiver. The

transfer is controlled by the Master device which

generates the serial clock and all START and STOP

conditions for bus access. The CAT9555 operates as a

Slave device. Both the Master device and Slave device

can operate as either transmitter or receiver, but the

Master device controls which mode is activated.

I2C Bus Protocol

The features of the I2C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition

(Figure 5).

START and STOP Conditions

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT9555 monitors the

SDA and SCL lines and will not respond until this

condition is met.

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

Device Addressing

After the bus Master sends a START condition, a slave

address byte is required to enable the CAT9555 for a

read or write operation. The four most significant bits of

the slave address are fixed as binary 0100 (Figure 6).

The CAT9555 uses the next three bits as address bits.

The address bits A2, A1 and A0 are used to select which

device is accessed from maximum eight devices on the

same bus. These bits must compare to their hardwired

input pins. The 8th bit following the 7-bit slave address

is the R/

W bit that specifies whether a read or write

operation is to be performed. When this bit is set to “1”,

a read operation is initiated, and when set to “0”, a write

operation is selected.

Following the START condition and the slave address

byte, the CAT9555 monitors the bus and responds with

an acknowledge (on the SDA line) when its address

matches the transmitted slave address. The CAT9555

then performs a read or a write operation depending on

the state of the R/

W bit.

START

CONDITION

STOP

CONDITION

SDA

SCL

0

1

0

A2

A1

A0

R/W

SLAVE ADDRESS

FIXED

PROGRAMMABLE

HARDWARE

SELECTABLE

Figure 6. CAT9555 Slave Address

Número de pieza similar - CAT9555WI

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Descripción similar - CAT9555WI

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
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