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ISL45042A Datasheet(PDF) 2 Page - Intersil Corporation |
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ISL45042A Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 8 page 2 FN6158.3 August 29, 2007 Pin Descriptions PIN FUNCTION OUT Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128. See SET pin function description for the maxim adjustable sink current setting. AVDD High-Voltage Analog Supply. Connects to top of external resistor divider to determine the VCOM voltage. Typically 10V to 20V. Bypass to GND with 0.1µF de-coupling capacitor. N/C No Connect. Not internally connected. GND Ground connection. VDD ISL45042A power supply input. Bypass to GND with 0.1µF de-coupling capacitor. CTL Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-Bit counter. See EEPROM Programming section for details. CE Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent further adjustment or programming (note: the CE pin has an internal pull down resistor). SET Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. Block Diagram ISL45042A DIGITAL INTERFACE WITH THRESHOLD SENSORS UP/DOWN COUNTER WITH PRESET LATCHES EEPROM OR NVL MEMORY ANALOG DCP AND CURRENT OUTPUT BLOCK AVDD IOUT SET CTL CE VDD GND UP DWN PWRUP PRGM POR POR PRGM IBIAS READ PRGM MEMORY 400k Ω TO 500k Ω ISL45042A |
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