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L9825 Datasheet(PDF) 5 Page - STMicroelectronics

No. de pieza L9825
Descripción Electrónicos  Octal Low-side Driver For Resistive and Inductive Loads With Serial / Parallel Input Control, Output Protection and Diagnostic
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9825 Datasheet(HTML) 5 Page - STMicroelectronics

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L9825
Diagnostics
VDG
Diagnostic threshold voltage
0.32·VCC
0.4·VCC
V
IOL
Open load detection sink current
Vout = VDG
20
100
µA
tdf
Diagnostic detection filter time for
output 1 & 2 on each diagnostic
condition
15
50
µs
Outputs timing
tdon1
Turn ON delay of OUT 1 and 2
NON1, 2 = 50% to VOUT = 0.9·Vbat
NCS = 50% to VOUT = 0.9·Vbat
5µs
tdon2
Turn ON delay of OUT 3 to 8
NCS = 50% to VOUT = 0.9·Vbat
10
µs
tdoff
Turn OFF delay of OUT 1 to 8
NCS = 50% to VOUT = 0.1·Vbat
NON1, 2 = 50% to VOUT = 0.1·Vbat
10
µs
dUon1/dt
Turn ON voltage slew-rate
For output 3 to 8; 90% to 30% of
Vbat; RL = 500Ω; Vbat = 16V
0.7
3.5
V/µs
dUon2/dt
Turn ON voltage slew-rate
For output 1 and 2; 90% to 30%
of Vbat; RL = 500Ω; Vbat = 16V
2
10
V/µs
dUoff1/dt
Turn OFF voltage slew-rate
For output 1 to 8; 30% to 90% of
Vbat; RL = 500Ω; Vbat = 16V
2
10
V/µs
dUoff2/dt
Turn OFF voltage slew-rate
For output 1 to 8; 30% to 80% of
Vbat; RL = 500Ω; Vbat = 0.9 · Vclp
2
15
V/µs
Serial diagnostic link (Load capacitor at SDO = 100pF)
fclk
Clock frequency
50% duty cycle
3
MHz
tclh
Minimum time CLK = HIGH
160
ns
tcll
Minimum time CLK = LOW
160
ns
tpcld
Propagation delay
CLK to data at SDO valid
4.9V
≤ VCC ≤ 5.1V
100
ns
tcsdv
NCS = LOW to data at SDO
active
100
ns
tsclch
CLK low before NCS low
Setup time CLK to NCS change H/L
100
ns
thclcl
CLK change L/H after NCS = low
100
ns
tscld
SDI input setup time
CLK change H/L after SDI data
valid
20
ns
thcld
SDI input hold time
SDI data hold after CLK change H/L
20
ns
tsclcl
CLK low before NCS high
150
ns
thclch
CLK high after NCS high
150
ns
tpchdz
NCS L/H to output data float
100
ns
NCS pulse filter time
Multiple of 8 CLK cycles
ELECTRICAL CHARACTERISTCS (continued)
(4.5V
≤ VCC ≤ 5.5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit


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