W209C
PRELIMINARY
Document #: 38-07171 Rev. *A
Page 2 of 16
I
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
REF2x/FS3
1
I/O
Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock out-
put. This pin also serves as the select strap to determine device operating frequency
as described in Table 1.
X1
3
I
Crystal Input: This pin has dual functions. It can be used as an external 14.318-
MHz crystal connection or as an external reference frequency input.
X2
4
I
Crystal Output: An input connection for an external 14.318-MHz crystal connec-
tion. If using an external reference, this pin must be left unconnected.
FS0*/PCI0
10
I/O
PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
FS1*/PCI1
11
I/O
PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
FS2*/PCI2
12
I/O
PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI3:7
14, 15, 17, 18,
19
O
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually
turned off via SMBus interface.
3V66_0:1
7,8
O
66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled
by FS0:4 (see Table 1).
48MHz_0
21
O
48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.
FS4*/
48MHz_1
22
I/O
48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread
spectrum clock output. This pin also serves as the select strap to determine device
operating frequency as described in Table 1.
SIO/
24_48#MHz*
23
I/O
Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.
During power up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
PWRDWN#
29
I
Power Down Control: LVTTL-compatible input that places the device in power-
down mode when held LOW.
CPU0:1
45, 44
O
CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:4. Voltage swing is set by VDDQ2.
SDRAM0:7,
DCLK
41, 40, 39, 37,
36, 35, 33, 32,
31
O
SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The operating fre-
quency is controlled by FS0:4 (see Table 1).
APIC
47
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
25
I/O
Data pin for SMBus circuitry.
SCLK
28
I
Clock pin for SMBus circuitry.
VDDQ3
2, 6, 16, 24, 27,
34, 42
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
VDDQ2
46, 48
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
GND
5, 9, 13, 20, 26,
30, 38, 43,
G
Ground Connections: Connect all ground pins to the common system ground
plane.
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